Bluespec sponsored by Bluespec, Inc.
Description: Bluespec's products enable ASIC and FPGA designers to appreciably reduce design time, bugs, verification resources and re-spins that contribute to product delays and escalating costs. | |
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Intel® 41210 Serial to Parallel PCI Bridge sponsored by Intel
Description:
Designed specifically for Host Bus Adapters (HBAs) and add-in cards, the Intel® 41210 Serial to Parallel PCI Transparent Bridge chip connects parallel bus PCI and PCI-X technology-based peripheral card applications.
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Synopsys LEDA® sponsored by Synopsys, Inc.
Description: Synopsys LEDA® is a programmable coding and design guideline checker that delivers full chip mixed-language (Verilog and VHDL) capabilities to speed development of complex system-on-chip (SoC) designs. | |
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Synopsys Library Compiler™ sponsored by Synopsys, Inc.
Description: Library Compiler provides library information including cell timing, function, power, test and physical data for optimized tool performance while meeting technology requirement. | |
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Synopsys Module Compiler sponsored by Synopsys, Inc.
Description: Module Compiler™ simplifies and automates datapath synthesis allowing users to achieve high-performance designs in a much shorter time. | |
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Synopsys NanoSim™ sponsored by Synopsys, Inc.
Description: NanoSim™ is an advanced circuit simulation solution for memory and mixed-signal verification that combines best-in-class circuit simulation technologies from existing Synopsys circuit simulators TimeMill and PowerMill. | |
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Synopsys PathMill® sponsored by Synopsys, Inc.
Description: PathMill® is the de facto standard transistor-level static-timing analysis tool targeted at designers of complex microprocessor and DSP chips. | |
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Synopsys Physical Compiler™ sponsored by Synopsys, Inc.
Description: Building upon the industry-standard Design Compiler tool allows Physical Compiler to work seamlessly with Synopsys’ power, datapath, test and DesignWare tools in addition to the built-in clock tree synthesis and routing capabilities. | |
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Synopsys Power Compiler™ sponsored by Synopsys, Inc.
Description: Power Compiler™ automatically minimizes power consumption and enables pre-synthesis power estimation for budget analysis and architectural explorations that result in lower power and shorter design cycle. | |
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Synopsys PowerArc® sponsored by Synopsys, Inc.
Description: PowerArc is a stand-alone cell library power characterization tool. | |
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Synopsys PowerMill® sponsored by Synopsys, Inc.
Description: PowerMill® is an accurate, high speed, high capacity circuit simulator. | |
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Synopsys PrimePower sponsored by Synopsys, Inc.
Description: PrimePower provides RT- and gate-level power analysis and debugging to help designers meet power specs, reduce packaging costs and reduce excess power. | |
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Synopsys PrimeTime Signal Integrity sponsored by Synopsys, Inc.
Description: PrimeTime Signal Integrity (SI) is a full-chip, static crosstalk analysis tool targeted for analysis of signal integrity effects found in ultra-deep submicron designs. | |
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Synopsys PrimeTime® sponsored by Synopsys, Inc.
Description: PrimeTime’s integration into logical and physical design flows enables quick debugging of complex timing problems and speeds timing closure. | |
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Synopsys RailMill® sponsored by Synopsys, Inc.
Description: RailMill® is a production-proven transistor level power network analysis tool that enables designers to analyze voltage (IR) drop and electromigration (EM) problems in today’s high performance deep-submicron IC digital and mixed signal designs. | |
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MORE SPECIFIC TOPICS:
IP Core